8251 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART)
The 8251 is a USART for serial data communication.As a peripheral device of a microcomputer system, the 8251
receives parallel data from the CPU and transmits serial data
after conversion. This device also receives serial data from the
outside and transmits parallel data to the CPU after conversion.
8251 USART Logical Diagram 8251 USART Pin Description
D 0 to D 7 (l/O terminal) This is bidirectional data bus which
receive control words and transmits data from the CPU and
sends status words and received data to CPU. RESET (Input terminal)
A "High" on this input forces the 8251 into "reset status."
The device waits for the writing of "mode instruction."
The min. reset width is six clock inputs during the
operating status of CLK.
CLK (Input terminal) CLK signal is used to generate internal
device timing. CLK signal is independent of RXC or TXC.
However, the frequency of CLK must be greater than 30 times
the RXC and TXC at Synchronous mode and Asynchronous
"x1" mode, and must be greater than 5 times at Asynchronous
"x16" and "x64" mode. WR (Input terminal) This is the
"active low" input terminal which receives a signal for
writing transmit data and control words from the CPU
into the 8251. RD (Input terminal) This is the "active low"
input terminal which receives a signal for reading receive
data and status words from the 8251. C/D (Input terminal)
This is an input terminal which receives a signal for selecting
data or command words and status words when the 8251
is accessed by the CPU. If C/D = low, data will be accessed.
If C/D = high, command word or status word will be accessed.
CS (Input terminal) This is the "active low" input terminal
which selects the 8251 at low level when the CPU accesses.
Note:
The device won’t be in "standby status"; only setting CS = High.
TXD (output terminal) This is an output terminal for transmitting
data from which serial-converted data is sent out.
The device is in "mark status" (high level) after resetting or
during a status when transmit is disabled. It is also possible
to set the device in "break status" (low level) by a command.
TXRDY (output terminal) This is an output terminal which
indicates that the 8251is ready to accept a transmitted data
character. But the terminal is always at low level if
CTS = high or the device was set in "TX disable status"
by a command. Note: TXRDY status word indicates that
transmit data character is receivable, regardless of CTS
or command. If the CPU writes a data character, TXRDY
will be reset by the leading edge or WR signal.
TXEMPTY (Output terminal)
This is an output terminal which indicates that the 8251
has transmitted all the characters and had no data character.
In "synchronous mode," the terminal is at high level,
if transmit data characters are no longer remaining and
sync characters are automatically transmitted. If the
CPU writes a data character, TXEMPTY will be reset
by the leading edge of WR signal. Note : As the transmitter
is disabled by setting CTS "High" or command, data
written before disable will be sent out. Then TXD and
TXEMPTY will be "High". Even if a data is written
after disable, that data is not sent out and TXE will be
"High".After the transmitter is enabled, it sent out.
TXC (Input terminal) This is a clock input signal
which determines the transfer speed of transmitted data.
In "synchronous mode," the baud rate will be the same as the
frequency of TXC. In "asynchronous mode", it is possible to
select the baud rate factor by mode instruction.
It can be 1, 1/16 or 1/64 the TXC. The falling edge of TXC sifts the
serial data out of the 8251. RXD (input terminal) This is a
terminal which receives serial data. RXRDY (Output terminal)
This is a terminal which indicates that the 8251 contains a character
that is ready to READ. If the CPU reads a data character, RXRDY
will be reset by the leading edge of RD signal. Unless the CPU
reads a data character before the next one is received completely,
the preceding data will be lost. In such a case, an overrun
error flag status word will be set. RXC (Input terminal)
This is a clock input signal which determines the transfer
speed of received data. In "synchronous mode," the
baud rate is the same as the frequency of RXC.
In "asynchronous mode," it is possible to select the baud
rate factor by mode instruction. It can be 1, 1/16, 1/64 the
RXC. SYNDET/BD (Input or output terminal) This is a terminal
whose function changes according to mode. In "internal
synchronous mode." this terminal is at high level, if sync
characters are received and synchronized. If a status word
is read, the terminal will be reset. In "external synchronous
mode, "this is an input terminal. A "High" on this input forces
the 8251 to start receiving data characters.
In "asynchronous mode," this is an output terminal which generates
"high level"output upon the detection of a "break" character
if receiver data contains a "low-level" space between the stop
bits of two continuous characters. The terminal will be
reset, if RXD is at high level. After Reset is active, the
terminal will be output at low level. DSR (Input terminal)
This is an input port for MODEM interface. The input status of
the terminal can be recognized by the CPU reading status words.
DTR (Output terminal) This is an output port for MODEM
interface. It is possible to set the status of DTR by a command.
CTS (Input terminal) This is an input terminal for MODEM
interface which is used for controlling a transmit circuit.
The terminal controls data transmission if the device is
set in "TX Enable" status by a command. Data is transmitable
if the terminal is at low level. RTS (Output terminal)
This is an output port for MODEM interface.
It is possible to set the status RTS by a command.
8251 USART Block Diagram
Block diagram of the 8251 USART(Universal Synchronous Asynchronous Receiver Transmitter)
Block Diagram of Transmitter and Receiver Section
Transmitter section:
1. The transmitter section accepts parallel data from
CPU and converts them into serial data.
2. The transmitter section is double buffered,
i.e., it has a buffer register to hold an 8-bit parallel data and
another register called output register to convert the parallel
data into serial bits.
3. When output register is empty, the data is transferred
from buffer to output register. Now the processor
can again load another data in buffer register.
4. If buffer register is empty, then TxRDY is goes to high.
5. If output register is empty then TxEMPTY goes to high.
6. The clock signal, TxC (low) controls the rate at which
the bits are transmitted by the USART.
7. The clock frequency can be 1,16 or 64 times the baud rate.
Receiver Section:
1. The receiver section accepts serial data and convert them into parallel data
2. The receiver section is double buffered, i.e., it has an
input register to receive serial data and convert to parallel,
and a buffer register to hold the parallel data.
3. When the RxD line goes low, the control logic
assumes it as a START bit, waits for half a bit time
and samples the line again.
4. If the line is still low, then the input register accepts the
following bits, forms a character and loads it into the buffer register.
5. The CPU reads the parallel data from the buffer register.
6. When the input register loads a parallel data to buffer register, the RxRDY line goes high.
7. The clock signal RxC (low) controls the rate at
which bits are received by the USART.
8. During asynchronous mode, the signal
SYNDET/BRKDET will indicate the break in the data transmission.
9. During synchronous mode, the signal SYNDET/BRKDET
will indicate the reception of synchronous character.
Intitialzing the 8251 The 8251 functional configuration is programed by software. Operation between the 8251 and a CPU is executed by program control. Table 1 shows the operation between a CPU and the device. Table 1 Operation between a CPU and 8251
Control Words There are two types of control word.
1. Mode instruction (setting of function)
2. Command (setting of operation)
1) Mode Instruction Mode instruction is used for setting the
function of the 8251. Mode instruction will be in
"wait for write" at either internal reset or external reset.
That is, the writing of a control word after resetting will
be recognized as a "mode instruction."
Items set by mode instruction are as follows:
• Synchronous/asynchronous mode
• Stop bit length (asynchronous mode)
• Character length
• Parity bit
• Baud rate factor (asynchronous mode)
• Internal/external synchronization (synchronous mode)
• Number of synchronous characters (Synchronous mode)
The bit configuration of mode instruction
In the case of synchronous mode, it is necessary to write
one-or two byte sync characters.
If sync characters were written, a function will be set because
the writing of sync characters constitutes part of mode instruction.
2) Command Command is used for setting the operation of the 8251.
It is possible to write a command whenever necessary after writing a
mode instruction and sync characters
. Items to be set by command are as follows:
• Transmit Enable/Disable
• Receive Enable/Disable
• DTR, RTS Output of data.
• Resetting of error flag
• Sending to break characters
• Internal resetting
• Hunt mode (synchronous mode)
Status Word
It is possible to see the internal status of the 8251 by reading a status word.The bit configuration of status word
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